1. Field of the Invention
The invention relates generally to the field of 2T decoders, and in particular, to a 2T decoder for a synchronizing signal in a digital video recording and playback environment.
2. Description of Related Art
In the recording of signals and data, high storage density is desirable in order to accommodate the largest possible amount of signals, or data, in a predetermined storage area. This is particularly true for digital video recording. One means for increasing the effective storage density is the use of recording codes with the lowest possible redundancy. Nevertheless, strong low-frequency spectral components and large run length values must be accepted. During the reproduction of such signals from a magnetic tape, the partial-response Class IV equalization (PR4) is most commonly used today, in conjunction with a maximum-likelihood detector, for example of the Viterbi type. Together with the PR4 channel, this method of detection supplies a binary signal which is systematically changed as compared with the recording. The recorded bit pattern can be restored with the prior art circuit shown in FIG. 1. Since this is a recursive circuit, a single wrong bit leads to an infinite error propagation. It is therefore customary to use the circuit shown in FIG. 1 with an exclusive or (EXOR) gate and two D-type flip flops as encoders (2T encoders). Use of the symbol T herein means the duration of the period of the bit clock signal (clk). As a result, the recorded bit pattern is changed in such a way that the original bit pattern is produced at the output of the PR4 channel.
When equalization and detection circuits which supply the recorded signal are used in the reproduction of a signal recorded with 2T precoding, the precoding must be subsequently canceled by means of another circuit, such as the prior art circuit shown in FIG. 2. The circuit of FIG. 2 utilizes an EXOR gate 3 and two D-type flip flops 2, 6. Regeneration circuits such as that shown in FIG. 2, which are suitable for low-redundancy recordings and supply the recorded signal are described, for example, in DE OS 41 12 856.
Since the error propagation of the circuit shown in FIG. 2 is restricted to 2 bits, its use on the reproduction side is permissible. One disadvantage of the circuit is that the bit pattern recognition at the output of the circuit is not unambiguous. In other words, various bit patterns at the input of the circuit can generate the sought-after bit pattern at the output of the circuit. During recording, for example, the bit pattern of FIG. 3a generates the bit patterns of FIG. 3b or FIG. 3c at the output of the 2T encoder shown in FIG. 1, if the two flip flops of the encoder are in each case set to 0,0 or 1,1 at the beginning of the bit pattern. The signals of FIG. 3b and FIG. 3c are, for example, the agreed synchronization pattern of the recorded signal. The bit patterns of both FIGS. 3b and 3c produce the bit pattern of FIG. 3d at the output of the circuit shown in FIG. 2, which agrees with the original bit pattern of FIG. 3a, apart from 2 bits. However, the bit pattern of FIG. 3d is also generated by the bit patterns of FIG. 3e and FIG. 3f. This can lead to problems in the block synchronization of the reproduced signal.